Pcie Base Specification [upd] ⟶

| Gen | Raw Bit Rate | Encoding | Effective per Lane (x1) | | :--- | :--- | :--- | :--- | | 3.0 | 8 GT/s | 128b/130b | ~985 MB/s | | 4.0 | 16 GT/s | 128b/130b | ~1.97 GB/s | | 5.0 | 32 GT/s | NRZ | ~3.94 GB/s | | 6.0 | 64 GT/s | | ~7.56 GB/s |

Moving from NRZ to PAM4 (4-level signaling) and introducing FLIT (Flow Control Unit) mode, which removes the 128b/130b overhead entirely for better efficiency. Final Thoughts The PCIe Base Specification is a masterpiece of backward compatibility. You can plug a Gen 1 card from 2004 into a Gen 6 slot today. It will simply "link train" at the lowest common denominator. pcie base specification

For engineers, reading the spec directly (available from PCI-SIG for members) is intimidating—roughly 1,400 pages. But understanding the covers 90% of what you need to debug a failing link or design a compliant device. | Gen | Raw Bit Rate | Encoding

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